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1 ? fn8118.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005, 2006. all rights reserved all other trademarks mentioned are the property of their respective owners. x4043, x4045 4k, 512 x 8 bit cpu supervisor with 4kbit eeprom features ? selectable watchdog timer ?low v cc detection and reset assertion ?five standard reset threshold voltages ?adjust low v cc reset threshold voltage using special programming sequence ?reset signal valid to v cc = 1v ? low power cmos ?<20a max standby current, watchdog on ?<1a standby current, watchdog off ?3ma active current ? 4kbits of eeprom ?16-byte page write mode ?self-timed write cycle ?5ms write cycle time (typical) ? built-in inadvertent write protection ?power-up/power-down protection circuitry ?protect 0, 1/4, 1/2, all or 16, 32, 64 or 128 bytes of eeprom array with block lock ? protection ? 400khz 2-wire interface ? 2.7v to 5.5v power supply operation ? available packages ?8 ld soic ?8 ld msop ?8 ld pdip ? pb-free plus anneal available (rohs compliant) description the x4043/45 combines four popular functions, power-on reset control, watchdog timer, supply voltage supervision, and block lock protect serial eeprom memory in one pa ckage. this combination lowers system cost, reduces board space require- ments, and increases reliability. applying power to the device activates the power-on reset circuit which holds reset /reset active for a period of time. this allows the power supply and oscilla- tor to stabilize before the processor can execute code. the watchdog timer provides an independent protec- tion mechanism for microcontrollers. when the micro- controller fails to restart a timer within a selectable time out interval, the device activates the reset /reset signal. the user selects the interval from three preset values. once selected, the interval does not change, even after cycling the power. the device?s low v cc detection circuitry protects the user?s system from low volt age conditions, resetting the system when v cc falls below the minimum v cc trip point. reset /reset is asserted until v cc returns to proper operating level and stabilizes. five industry stan- dard v trip thresholds are avail able, however, intersil?s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the thresh- old for applications requiring higher precision. block diagram watchdog timer reset data register command decode & control logic sda scl v cc reset & watchdog timebase power-on and generation v trip + - reset (x4043) reset low voltage status register protect logic eeprom array watchdog transition detector wp v cc threshold reset logic block lock control 2kbits 1kb 1kb reset (x4045) data sheet march 16, 2006
2 fn8118.2 march 16, 2006 ordering information part number reset (active low) part marking part number reset (active high) part marking v cc range (v) v trip range (v) temp range (c) package x4043s8-4.5a x4043 al x4045s8-4.5a x4045 al 4.5-5.5 4.5-4.75 0 to 70 8 ld soic x4043s8z-4.5a (note) x4043 z al x4045s8z-4.5a (note) x4045 z al 0 to 70 8 ld soic (pb-free) x4043s8i-4.5a x4043 am x4045s8i-4.5a x4045 am -40 to 85 8 ld soic x4043s8iz-4.5a (note) x4043 z am x4045s8iz-4.5a (note) x4045 z am -40 to 85 8 ld soic (pb-free) x4043m8-4.5a ada x4045m8-4.5a adj 0 to 70 8 ld msop x4043m8z-4.5a (note) daz x4045m8z-4.5a (note) dbh 0 to 70 8 ld msop (pb-free) x4043m8i-4.5a adb x4045m8i-4.5a adk -40 to 85 8 ld msop x4043m8iz-4.5a (note) dau x4045m8iz-4.5a (note) dbe -40 to 85 8 ld msop (pb-free) x4043p-4.5a x4043p al x4045p-4.5a x4045p al 0 to 70 8 ld pdip x4043pz-4.5a (note) x4043p z al x4045pz-4.5a (note) x4045p z al 0 to 70 8 ld pdip (pb-free) x4043pi-4.5a x4043p am x4045pi-4.5a x4045p am -40 to 85 8 ld pdip x4043piz-4.5a (note) x4043p z am x4045piz-4.5a (note) x4045p z am -40 to 85 8 ld pdip (pb-free) x4043s8* x4043 x4045s8* x4045 4.5-5.5 4.25-4.5 0 to 70 8 ld soic x4043s8z* (note) x4043 z x4045s8z* (note) x4045 z 0 to 70 8 ld soic (pb-free) x4043s8i* x4043 i x4045s8i x4045 i -40 to 85 8 ld soic x4043s8iz* (note) x4043 z i x4045s8iz (note) x4045 z i -40 to 85 8 ld soic (pb-free) x4043m8 adc x4045m8 adl 0 to 70 8 ld msop x4043m8z* (note) daw x4045m8z (note) dbd 0 to 70 8 ld msop (pb-free) x4043m8i add x4045m8i adm -40 to 85 8 ld msop x4043m8iz (note) dar x4045m8iz (note) dba -40 to 85 8 ld msop (pb-free) x4043p x4043p z x4045p x4045p 0 to 70 8 ld pdip x4043pz (note) x4043p x4045pz (note) x4045p z 0 to 70 8 ld pdip (pb-free) x4043pi x4043p i x4045pi x4045p i -40 to 85 8 ld pdip x4043piz (note) x4043p z i x4045piz (note) x4045p z i -40 to 85 8 ld pdip (pb-free) x4043s8-2.7a* x4043 an x4045s8-2.7a x4045 an 2.7-5.5 2.85-3.0 0 to 70 8 ld soic x4043s8z-2.7a* (note) x4043 z an x4045s8z-2.7a (note) x4045 z an 0 to 70 8 ld soic (pb-free) x4043s8i-2.7a* x4043 ap x4045s8i-2.7a x4045 ap -40 to 85 8 ld soic x4043s8iz-2.7a* (note) x4043 z ap x4045s8iz-2.7a (note) x4045 z ap -40 to 85 8 ld soic (pb-free) x4043m8-2.7a ade x4045m8-2.7a and 0 to 70 8 ld msop x4043m8z-2.7a (note) day x4045m8z-2.7a (note) dbg 0 to 70 8 ld msop (pb-free) x4043m8i-2.7a adf x4045m8i-2.7a ado -40 to 85 8 ld msop x4043m8iz-2.7a (note) dat x4045m8iz-2.7a (note) dbc -40 to 85 8 ld msop (pb-free) x4043p-2.7a x4043p an x4045p-2.7a x4045p an 0 to 70 8 ld pdip x4043pz-2.7a (note) x4043p z an x4045pz-2.7a (note) x4045p z an 0 to 70 8 ld pdip (pb-free) x4043pi-2.7a x4043p ap x4045pi-2.7a x4045p ap -40 to 85 8 ld pdip x4043piz-2.7a (note) x4043p z ap x4045piz-2.7a (note) x4045p z ap -40 to 85 8 ld pdip (pb-free) x4043, x4045
3 fn8118.2 march 16, 2006 x4043s8-2.7* x4043 f x4045s8-2.7* x4045 f 2.7-5.5 2.55-2.7 0 to 70 8 ld soic x4043s8z-2.7* (note) x4043 z f x4045s8z-2.7* (note) x4045 z f 0 to 70 8 ld soic (pb-free) x4043s8i-2.7 x4043 g x4045s8i-2.7 x4045 g -40 to 85 8 ld soic x4043s8iz-2.7 (note) x4043 z g x4045s8iz-2.7 (note) x4045 z g -40 to 85 8 ld soic (pb-free) x4043m8-2.7 adg x4045m8-2.7 adp 0 to 70 8 ld msop x4043m8z-2.7 (note) dax x4045m8z-2.7 (note) dbf 0 to 70 8 ld msop (pb-free) x4043m8i-2.7 adh x4045m8i-2.7 adq -40 to 85 8 ld msop x4043m8iz-2.7(note) das x4045m8iz-2.7 (note) dbb -40 to 85 8 ld msop (pb-free) x4043p-2.7 x4043p f x4045p-2.7 x4045p f 0 to 70 8 ld pdip x4043pz-2.7 (note) x4043p z f x4045pz-2.7 (note) x4045p z f 0 to 70 8 ld pdip (pb-free) x4043pi-2.7 x4043p g x4045pi-2.7 x4045p g -40 to 85 8 ld pdip x4043piz-2.7 (note) x4043p z g x4045piz-2.7 (note) x4045p z g -40 to 85 8 ld pdip (pb-free) *add "t1" suffix for tape and reel. note: intersil pb-free plus anneal products em ploy special pb-free material sets; molding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ordering information part number reset (active low) part marking part number reset (active high) part marking v cc range (v) v trip range (v) temp range (c) package x4043, x4045
4 fn8118.2 march 16, 2006 the memory portion of the device is a cmos serial eeprom array with intersil?s block lock protection. the array is internally organized as x 8. the device features an 2-wire interface and software protocol allowing operation on an i 2 c bus. the device utilizes intersil?s proprietary direct write ? cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. pin configuration nc v ss v cc sda scl 3 2 4 1 6 7 5 8 nc wp reset 8-pin jedec soic, msop, pdip pin (soic/msop/dip) name function 1 nc no internal connections 2 nc no internal connections 3 reset /reset reset output . reset is an active low, open drain output which goes active whenever v cc falls below v trip . it will remain active until v cc rises above the v trip for t purst . reset /reset goes active if the watchdog timer is enabled and sda remains either high or low longer than the selectable watchdog time out period. reset /reset goes active on power-uppower-up and remains active for 250ms after the power supply stabilizes. reset is an active high open drain output. an external pull up re sistor is required on the reset /reset pin. 4v ss ground 5sda serial data. sda is a bidirectional pin used to transfer data into and out of the device. it has an open drain output and may be wire ored with other open drain or open collector outputs. this pin requires a pull up resistor and the input buffer is always active (not gated). 6scl serial clock. the serial clock input controls the serial bus timing for data input and output. 7wp write protect. wp high prevents writes to any location in the device (including the control register). connect wp pin to v ss when it is not used. 8v cc supply voltage x4043, x4045
5 fn8118.2 march 16, 2006 principles of operation power-on reset application of power to the x4043/45 activates a power-on reset circuit that pulls the reset /reset pin active. this signal provides several benefits. ? it prevents the system micr oprocessor from starting to operate with insufficient voltage. ? it prevents the processor from operating prior to sta- bilization of the oscillator. ? it allows time for an fpga to download its configura- tion prior to initialization of the circuit. when v cc exceeds the device v trip threshold value for 200ms (nominal) the circuit releases reset /reset allowing the system to begin operation. low voltage monitoring during operation, the x4043/45 monitors the v cc level and asserts reset /reset if supply voltage falls below a preset minimum v trip . the reset /reset signal prevents the microprocessor from operating in a power fail or brownout condition. the reset /reset signal remains active until the voltage drops below 1v. it also remains active until v cc returns and exceeds v trip for 200ms. watchdog timer the watchdog timer circuit monitors the microproces- sor activity by monitoring the sda and scl pins. a standard read or write sequence to any slave address byte restarts the watchdog timer and prevents the (reset/reset ) signal going active. a minimum sequence to reset the watchdog timer requires four microprocessor intructions na mely, a start, clock low, clock high and stop. (see page 18) the state of two nonvolatile control bits in t he status register determine the watchdog timer period. the microprocessor can change these watchdog bits, or they may be ?locked? by tying the wp pin high. figure 1. watchdog restart eeprom inadvertent write protection when reset /reset goes active as a result of a low voltage condition (v cc < v trip ), any in-progress com- munications are terminated. while v cc < v trip , no new communications are allowed and no nonvolatile write operation can start. nonvolat ile writes in-progress when reset /reset goes active are allowed to finish. additional protection mechanisms are provided with memory block lock and the write protect (wp) pin. these are discussed elsewhere in this document. v trip programming the x4043/45 is shipped with a standard v cc thresh- old (v trip ) voltage. this valu e will not change over normal operating and storage conditions. however, in applications where the standard v trip is not exactly right, or if higher precision is needed in the v trip value, the x4043/45 threshold may be adjusted. the procedure is described below, and uses the applica- tion of a high voltage control signal. figure 2. set v trip level sequence (v cc = desired v trip values wel bit set) scl sda .6s 1.3s start stop reset wdt 01234567 scl sda a0h 01234567 01h wp v p = 15-18v 01234567 00h x4043, x4045
6 fn8118.2 march 16, 2006 setting a v trip voltage there are two procedures used to set the threshold voltages (v trip ), depending if the threshold voltage to be stored is higher or lower than the present value. for example, if the present v trip is 2.9 v and the new v trip is 3.2 v, the new voltage can be stored directly into the v trip cell. if however, the new setting is to be lower than the present setting, then it is necessary to ?reset? the v trip voltage before setting the new value. setting a higher v trip voltage to set a v trip threshold to a new voltage which is higher than the present threshold, the user must apply the desired v trip threshold voltage to the v cc . then, a programming voltage (vp) must be applied to the wp pin before a start condition is set up on sda. next, issue on the sda pin the slave address a0h, followed by the byte address 01h for v trip and a 00h data byte in order to program v trip . the stop bit following a valid write oper ation initiates the program- ming sequence. wp pin must then be brought low to complete the operation. to check if the v trip has been set, first power-down the device. slowly ramp up v cc and observe when the output, reset (4043) or reset (4 045) switches. the voltage at which this occurs is the v trip (actual) (see figure 2). c ase a now if the desired v trip is greater than the v trip (actual), then add t he difference between v trip (desired) - v trip (actual) to the original v trip desired. this is your new v trip that should be applied to v cc and the whole sequence should be repeated again (see figure 5). c ase b now if the v trip (actual), is higher than the v trip (desired), perform the reset sequence as described in the next section. the new v trip voltage to be applied to v cc will now be: v trip (desired) - (v trip (actual)-v trip (desired)). note: this operation does not corrupt the memory array. setting a lower v trip voltage in order to set v trip to a lower voltage than the present value, then v trip must first be ?reset? accord- ing to the procedure described below. once v trip has been ?reset?, then v trip can be set to the desired volt- age using the procedure described in ?setting a higher v trip voltage?. resetting the v trip voltage to reset a v trip voltage, apply the programming volt- age (vp) to the wp pin before a start condition is set up on sda. next, issue on the sda pin the slave address a0h followed by the byte address 03h fol- lowed by 00h for the data byte in order to reset v trip . the stop bit following a valid write operation initiates the programming sequence. pin wp must then be brought low to complete the operation. after being reset, the value of v trip becomes a nomi- nal value of 1.7v or lesser. note: this operation does not corrupt the memory array. x4043, x4045
7 fn8118.2 march 16, 2006 figure 3. reset v trip level sequence (v cc > 3v. wp = 15-18v, wel bit set) figure 4. sample v trip reset circuit 01234567 scl sda 01234567 wp v p = 15-18v 01234567 a0h 03h 00h 1 2 3 4 8 7 6 5 x4043 v trip adj. v p reset 4.7k sda scl c adjust run x4043, x4045
8 fn8118.2 march 16, 2006 figure 5. v trip programming sequence control register the control register provides the user a mechanism for changing the block lock and watchdog timer settings. the block lock and watchdog timer bits are nonvolatile and do not change when power is removed. the control register is accessed with a special pream- ble in the slave byte (1011) and is located at address 1ffh. it can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. prior to writ ing to the control register, the wel and rwel bits must be set using a two step process, with the whole sequence requiring 3 steps. see "writing to the control register". the user must issue a stop after sending this byte to the register to initiate the nonvolatile cycle that stores wd1, wd0, bp2, bp1, and bp0. the x4043/45 will not acknowledge any data bytes written after the first byte is entered. v trip programming power-down actual v trip ? desired v trip done set higher v trip sequence error < mde ? | error | < | mde | yes no error > mde + the device desired present value ? v trip < execute no yes execute v trip reset sequence set v cc = desired v trip new v cc applied = old v cc applied + | error | new v cc applied = old v cc applied ? | error | execute reset v trip sequence output switches? let: mde = maximum desired error mde + desired value mde ? acceptable error range error = actual ? desired (reset ) ramp v cc = error x4043, x4045
9 fn8118.2 march 16, 2006 the state of the control register can be read at any time by performing a random read at address 1ffh, using the special preamble. only one byte is read by each register read operation. the x4043/45 resets itself after the first byte is read. the master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation. rwel: register write enable latch (volatile) the rwel bit must be set to ?1? prior to a write to the control register. wel: write enable latch (volatile) the wel bit controls the access to the memory and to the register during a write operation. this bit is a vola- tile latch that powers up in the low (disabled) state. while the wel bit is low, writes to any address, including any control regi sters will be ignored (no acknowledge will be issued after the data byte). the wel bit is set by writing a ?1? to the wel bit and zeroes to the other bits of the control register. once set, wel remains set until eith er it is reset to 0 (by writing a ?0? to the wel bit and zeroes to the other bits of the control register) or until the part powers up again. writes to the wel bi t do not cause a nonvolatile write cycle, so the device is ready for the next opera- tion immediately after the stop condition. bp2, bp1, bp0: block pr otect bits (nonvolatile) the block protect bits, bp2, bp1 and bp0, determine which blocks of the array are write protected. a write to a protected block of memory is ignored. the block pro- tect bits will prevent write operations to one of eight segments of the array. wd1, wd0: watchdog timer bits the bits wd1 and wd0 control the period of the watchdog timer. the options are shown below. writing to the control register changing any of the nonvolatile bits of the control reg- ister requires the following steps: ? write a 02h to the control register to set the write enable latch (wel). this is a volatile operation, so there is no delay after the write. (operation pre- ceeded by a start and ended with a stop). ? write a 06h to the contro l register to set both the register write enable latch (rwel) and the wel bit. this is also a volatile cy cle. the zeros in the data byte are required. (operation preceeded by a start and ended with a stop). ? write a value to the control register that has all the control bits set to the des ired state. this can be rep- resented as 0xys t 01 r in binary, where xy are the wd bits, and rst are the bp bits. (operation pre- ceeded by a start and ended with a stop). since this is a nonvolatile write cycle it will take up to 10ms to complete. the rwel bit is reset by this cycle and the sequence must be repeated to change the non- volatile bits again. if bit 2 is set to ?1? in this third step ( 0xys t 11 r ) then the rwel bit is set, but the wd1, wd0, bp2, bp1 and bp0 bi ts remain unchanged. writing a second byte to the control register is not allowed. doing so aborts the write operation and returns a nack. ? a read operation occurring between any of the previ- ous operations will not inte rrupt the regi ster write operation. ? the rwel bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. to illustrate, a sequ ence of writes to the device con- sisting of [02h, 06h, 02h] will reset all of the nonvola- tile bits in the control regist er to 0. a sequence of [02h, 06h, 06h] will leave the nonvolatile bits unchanged and the rwel bit remains set. 76 5 4 3 2 1 0 0 wd1 wd0 bp1 bp0 rwel wel bp2 bp2 bp1 bp0 protected addresses (size) array lock 0 0 0 none (factory setting) none 0 0 1 180h - 1ffh (128 bytes ) upper 1/4 (q4) 0 1 0 100h - 1ffh (256 bytes ) upper 1/2 (q3,q4) 0 1 1 000h - 1ffh (512 bytes) full array (all) 1 0 0 000h - 00fh (16 bytes) first page (p1) 1 0 1 000h - 01fh (32 bytes) first 2 pgs (p2) 1 1 0 000h - 03fh (64 bytes) first 4 pgs (p4) 1 1 1 000h - 07fh (128 bytes) first 8 pgs (p8) wd1 wd0 watchdog time out period 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled (factory setting) x4043, x4045
10 fn8118.2 march 16, 2006 serial interface serial interface conventions the device supports a bidirectional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the mast er always initiates data transfers, and provides the clock for both transmit and receive operations. therefore, the devices in this fam- ily operate as slaves in all applications. serial clock and data data states on the sda line can change only during scl low. sda state cha nges during scl high are reserved for indicating start and stop conditions. see figure 6. figure 6. valid data changes on the sda bus serial start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device contin uously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. see figure 7. serial stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda when scl is high. the stop condi tion is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has rel eased the bus. see figure 6. figure 7. valid start and stop conditions serial acknowledge acknowledge is a software convention used to indi- cate successful data transf er. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during t he ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 8. the device will respond wit h an acknowledge after recognition of a start condit ion and if the correct device identifier and select bits are contained in the slave address byte. if a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. the device will acknowledge all incoming data and address bytes, except for the slave address byte when the device identifier and/or select bits are incorrect. in the read mode, the device will transmit eight bits of data, release the sda line, then monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generate d by the master, the device will continue to transmit da ta. the device will terminate further data transmissions if an acknowledge is not detected. the master must then issue a stop condition to return the device to standby mode and place the device into a known state. scl sda data stable data change data stable scl sda start stop x4043, x4045
11 fn8118.2 march 16, 2006 figure 8. acknowledge response from receiver x4043/45 addressing slave address byte following a start condition, the master must output a slave address byte. this byte consists of several parts: ? a device type identifier that is ?1010? to access the array and ?1011? to access the control register. ? two bits of ?0?. ? one bit that becomes the msb of the address. ? one bit of the slave command byte is a r/w bit. the r/w bit of the slave address byte defines the opera- tion to be performed. when the r/w bit is a one, then a read operation is selected. a zero selects a write operation. refer to figure 8. ? after loading the entire slave address byte from the sda bus, the device compares the input slave byte data to the proper slave byte. upon a correct compare, the device outputs an acknowledge on the sda line. word address the word address is either supplied by the master or obtained from an internal counter. the internal counter is undefined on a power-up condition. slave address byte figure 9. x4043/45 addressing operational notes the device powers-up in the following state: ? the device is in the low power standby state. ? the wel bit is set to ?0?. in this state it is not possi- ble to write to the device. ? sda pin is the input mode. ? reset signal is active for t purst . serial write operations byte write for a write operation, the device requires the slave address byte and a word address byte. this gives the master access to any one of the words in the array. after receipt of the word address byte, the device responds with an acknowledge, and awaits the next eight bits of data. after receiving the 8 bits of the data byte, the device again responds with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the device begins the inter- nal write cycle to the nonvolatile memory. during this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. the sda output is at high impedance. see figure 10. a write to a protected block of memory will suppress the acknowledge bit. data output from transmitter data output from receiver 8 1 9 start acknowledge scl from master array control reg. 1 1 0 0 1 1 0 1 00a8r/w a7 a6 a5 a4 a3 a2 a1 a0 word address slave byte x4043, x4045
12 fn8118.2 march 16, 2006 figure 10. byte write sequence page write the device is capable of a page write operation. it is initiated in the same manner as the byte write opera- tion; but instead of terminating the write cycle after the first data byte is transfer red, the master can transmit an unlimited number of 8-bit bytes. after the receipt of each byte, the device will respond with an acknowl- edge, and the address is internally incremented by one. the page address remains constant. when the counter reaches the end of the page, it ?rolls over? and goes back to ?0? on the same page. this means that the master can write 16 bytes to the page starting at any location on that page. if the master begins writing at location 10, and loads 12 bytes, then the first 5 bytes are written to locations 10 through 15, and the last 7 bytes are written to locations 0 through 6. after- wards, the address counter would point to location 7 of the page that was just written. if the master supplies more than 16 bytes of data, then new data over-writes the previous data, one byte at a time. figure 11. page write operation figure 12. writing 12-bytes to a 16-byte page starting at location 10 the master terminates the data byte loading by issu- ing a stop condition, whic h causes the device to begin the nonvolatile write cycle. as with the byte write opera- tion, all inputs are disabled until completion of the inter- nal write cycle. see figure 11 for the address, acknowledge, and data transfer sequence. stops and write modes stop conditions (that terminate write operations) must be sent by the master after sending at least 1 full data byte, plus the subsequent ack signal. if a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ack is sent, then the device will reset itself without performing t he write. the contents of the array will not be effected. s t a r t s t o p slave address byte address data a c k a c k a c k sda bus signals from the slave signals from the master 0 s t a r t s t o p slave address byte address data (n) a c k a c k sda bus signals from the slave signals from the master 0 data (1) a c k (1 n 16) a c k address address 10 5 bytes n-1 7 bytes address = 6 address pointer ends here addr = 7 x4043, x4045
13 fn8118.2 march 16, 2006 acknowledge polling the disabling of the inputs during nonvolatile cycles can be used to take advantage of the typical 5khz write cycle time. once the stop condition is issued to indicate the end of the master?s byte load operation, the device initiates the in ternal nonvolatile cycle. acknowledge polling can be initiated immediately. to do this, the master issues a start condition followed by the slave address byte for a write or read operation. if the device is still busy with the nonvolatile cycle then no ack will be returned. if the device has completed the write operation, an ack will be returned and the host can then proceed with the read or write operation. refer to the flow chart in figure 13. serial read operations read operations are initiated in the same manner as write operations with the exception that the r/w bit of the slave address byte is set to one. there are three basic read operations: current address reads, ran- dom reads, and sequential reads. current address read internally the device contains an address counter that maintains the address of the last word read incre- mented by one. therefore, if the last read was to address n, the next read operation would access data from address n+1. on power-up, the address of the address counter is undefined, requiring a read or write operation for initialization. upon receipt of the slave add ress byte with the r/w bit set to one, the device issues an acknowledge and then transmits the eight bits of the data byte. the master ter- minates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. refer to figure 13 for the address, acknowledge, and data transfer sequence. figure 13. acknowledge polling sequence it should be noted that the ninth clock cycle of the read operation is not a ?don?t care.? to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold sda high during the ninth clock cycle and th en issue a stop condition. figure 14. current address read sequence ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes nonvolatile cycle complete. continue command issue stop no continue normal read or write command sequence proceed yes s t a r t s t o p slave address data a c k sda bus signals from the slave signals from the master 1 x4043, x4045
14 fn8118.2 march 16, 2006 random read random read operation allows the master to access any memory location in the array. prior to issuing the slave address byte with the r/w bit set to one, the master must first perform a ?dummy? write operation. the master issues the star t condition and the slave address byte, receives an acknowledge, then issues the word address bytes. after acknowledging receipts of the word address bytes, the master immediately issues another start conditi on and the slave address byte with the r/w bit set to one. this is followed by an acknowledge from the device and then by the eight bit word. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. refer to figure 15 for the address, acknowledge, and data transfer sequence. figure 15. random address read sequence there is a similar operation, called ?set current address? where the device does no operation, but enters a new address into the address counter if a stop is issued instead of th e second start shown in fig- ure 14. the device goes into standby mode after the stop and all bus activity will be ignored until a start is detected. the next current address read operation reads from the newly loaded address. this operation could be useful if the master knows the next address it needs to read, but is not ready for the data. sequential read sequential reads can be initiated as either a current address read or random address read. the first data byte is transmitted as with the other modes; however, the master now responds wi th an acknowledge, indicat- ing it requires additional data. the device continues to output data for each acknowledge received. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. the data output is sequential, with the data from address n followed by the data from address n + 1. the address counter for read operations increments through all page and column addresses, allowing the entire memory con- tents to be serially read during one operation. at the end of the address space the counter ?rolls over? to address 0000 h and the device continues to output data for each acknowledge received. refer to figure 16 for the acknowledge and data transfer sequence. figure 16. sequential read sequence 0 slave address byte address a c k a c k s t a r t s t o p slave address data a c k 1 s t a r t sda bus signals from the slave signals from the master data (2) s t o p slave address data (n) a c k a c k sda bus signals from the slave signals from the master 1 data (n-1) (n is any integer greater than 1) data (1) a c k a c k x4043, x4045
15 fn8118.2 march 16, 2006 data protection the following circuitry has been included to prevent inadvertent writes: ? the wel bit must be set to allow write operations. ? the proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. ? a three step sequence is required before writing into the control register to change watchdog timer or block lock settings. ? the wp pin, when held high, prevents all writes to the array and the control register. ? communication to the device is inhibited as a result of a low voltage condition (v cc < v trip )any in- progress communication is terminated. ? block lock bits can protect sections of the memory array from write operations. symbol table waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x4043, x4045
16 fn8118.2 march 16, 2006 absolute maximum ratings temperature under bias ................... -65c to +135c storage temperature ............ ............ -65c to +150c voltage on any pin with respect to v ss ...................................... -1.0v to +7v d.c. output current ............................................... 5ma lead temperature (soldering, 10 seconds)........ 300c comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. d.c. operating characteristics (over the recommended operating cond itions unless otherwise specified.) notes: (1) the device enters the active state after any start, and re mains active until: 9 clock cyc les later if the device selec t bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or t wc after a stop ending a write operation. (2) the device goes into standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; t wc after a stop that initiates a nonvolatile cycle; or 9 cl ock cycles after any start that is not followed by the correct dev ice select bits in the slave addres s byte. (3) v il min. and v ih max. are for reference only and are not tested. symbol parameter v cc = 2.7 to 5.5v unit test conditions min. max. i cc1 (1) active supply current read 1.0 ma v il = v cc x 0.1, v ih = v cc x 0.9 f scl = 400khz i cc2 (1) active supply current write 3.0 ma i sb1 (2) standby current ac (wdt off) 1 a v il = v cc x 0.1, v ih = v cc x 0.9 f scl = 400khz, sda = open v cc = 1.22 x v cc min i sb2 (2) standby current dc (wdt off) 1 a v sda = v scl = v sb others = gnd or v sb i sb3 (2) standby current dc (wdt on) 20 a v sda =v scl = v sb others = gnd or v sb i li input leakage current 10 a v in = gnd to v cc i lo output leakage current 10 a v sda = gnd to v cc device is in standby v il (3) input low voltage -0.5 v cc x 0.3 v v ih (3) input nonvolatile v cc x 0.7 v cc + 0.5 v v hys schmitt trigger input hysteresis fixed input level v cc related level 0.2 .05 x v cc v v v ol output low voltage 0.4 v i ol = 3.0ma (2.7-5.5v) i ol = 1.8ma (2.0-3.6v) recommended operating conditions temperature min. max. commercial 0c 70c industrial -40c +85c option supply voltage limits -2.7 and -2.7a 2.7v to 5.5v blank and -4.5a 4.5v to 5.5v x4043, x4045
17 fn8118.2 march 16, 2006 capacitance (t a = 25c, f = 1.0 mhz, v cc = 5v) notes: (4) this parameter is periodically sampled and not 100% tested. equivalent a.c. load circuit a.c. test conditions a.c. characteristics (over recommended operating condit ions, unless otherwise specified) notes: (5) typical values are for t a = 25c and v cc = 5.0v (6) cb = total capacitance of one bus line in pf. symbol parameter max. unit test conditions c out (4) output capacitance (sda, reset /reset) 8 pf v out = 0v c in (4) input capacitance (scl, wp) 6 pf v in = 0v 5v 4.6k ? reset 100pf sda 1533 ? 100pf 5v for v ol = 0.4v and i ol = 3 ma input pulse levels 0.1 v cc to 0.9 v cc input rise and fall times 10ns input and output timing levels 0.5 v cc output load standard output load symbol parameter 100khz 400khz unit min. max. min. max. f scl scl clock frequency 0 100 0 400 khz t in pulse width suppression time at inputs n/a n/a 50 ns t aa scl low to sda data out valid 0.1 0.9 0.1 0.9 s t buf time the bus free before start of new transmission 4.7 1.3 s t low clock low time 4.7 1.3 s t high clock high time 4.0 0.6 s t su:sta start condition setup time 4.7 0.6 s t hd:sta start condition hold time 4.0 0.6 s t su:dat data in setup time 250 100 ns t hd:dat data in hold time 5.0 0 s t su:sto stop condition setup time 0.6 0.6 s t dh data output hold time 50 50 ns t r sda and scl rise time 1000 20 + .1cb (6) 300 ns t f sda and scl fall time 300 20 + .1cb (6) 300 ns t su:wp wp setup time 0.4 0.6 s t hd:wp wp hold time 0 0 s cb capacitive load for each bus line 400 400 pf x4043, x4045
18 fn8118.2 march 16, 2006 timing diagrams bus timing wp pin timing write cycle timing nonvolatile write cycle timing notes: (7) t wc is the time from a valid stop condition at the end of a writ e sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user , unless acknowledge polling is used. symbol parameter min. typ. (7) max. unit t wc (7) write cycle time 5 10 ms t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t aa t r t hd:wp scl sda in wp t su:wp clk 1 clk 9 slave address byte start scl sda t wc 8 th bit of last byte ack stop condition start condition x4043, x4045
19 fn8118.2 march 16, 2006 power-up and po wer-down timing reset output timing notes: (8) this parameter is periodically sampled and not 100% tested. symbol parameter min. typ. max. unit v trip reset trip point voltage, x4043/45-4.5a reset trip point voltage, x4043/45 reset trip point voltage, x4043/45-2.7a reset trip point voltage, x4043/45-2.7 4.5 4.25 2.85 2.55 4.62 4.38 2.92 2.62 4.75 4.5 3.0 2.7 v t purst power-up reset time out 100 200 400 ms t rpd (8) v cc detect to reset /reset 10 20 s t f (8) v cc fall time 20 mv/s t r (8) v cc rise time 20 mv/s v rvalid reset valid v cc 1v t wdo watchdog time out period, wd1 = 1, wd0 = 0 wd1 = 0, wd0 = 1 wd1 = 0, wd0 = 0 100 450 1 200 600 1.4 300 800 2 ms ms sec t rsp watchdog time restart pulse width 1 s t rst reset time out 100 200 400 ms v cc t purst t purst t r t f t rpd 0 volts v trip reset v rvalid reset v rvalid (x4043) (x4045) x4043, x4045
20 fn8118.2 march 16, 2006 watchdog time out for 2-wire interface v trip set/reset conditions < t wdo t rst (4043) reset sda start t wdo t rst scl start t rsp wdt restart start sda scl minimum sequence to reset wdt clockin (0 or 1) scl sda v cc (v trip ) wp t tsu t thd t vph t vps v p t wc t vpo 0 7 70 7 sets v trip 01h* 03h* resets v trip 0 start * all others reserved a0h 00h x4043, x4045
21 fn8118.2 march 16, 2006 v trip programming specifications: v cc = 2.0-5.5v; temperature = 25c parameter description min. max. unit t vps wp program voltage setup time 10 s t vph wp program voltage hold time 10 s t tsu v trip level setup time 10 s t thd v trip level hold (stable) time 10 s t wc v trip program cycle 10 ms t vpo program voltage off time before next cycle 1 ms v p programming voltage 15 18 v v tran v trip set voltage range 2.0 4.75 v v tv v trip set voltage variation after programming (-40 to +85c). -25 +25 mv t vps wp program voltage setup time 10 s x4043, x4045
22 fn8118.2 march 16, 2006 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 - 8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint x4043, x4045
23 fn8118.2 march 16, 2006 packaging information 0.118 0.002 (3.00 0.05) 0.040 0.002 (1.02 0.05) 0.150 (3.81) ref. 0.193 (4.90) 0.030 (0.76) 0.036 (0.91) 0.032 (0.81) 0.007 (0.18) 0.005 (0.13) 0.008 (0.20) 0.004 (0.10) 0.0216 (0.55) 7 typ. r 0.014 (0.36) 0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) typ. 8-lead miniature small outlin e gull wing package type m note: 1. all dimensions in inches and (millimeters) 0.220" 0.0256" typical 0.025" typical 0.020" typical 8 places footprint ref. x4043, x4045
24 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8118.2 march 16, 2006 packaging information note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional .073 (1.84) max. 0.325 (8.25) 0.300 (7.62) plane x4043, x4045
x4043 printer friendly version cpu supervisor with 4kbit eeprom datasheets, related docs & simulations description key features parametric data application diagrams related devices ordering information part no. design-in status temp. package msl price us $ x4043m8 active comm 8 ld msop 1 2.46 x4043m8-2.7 active comm 8 ld msop 1 2.46 x4043m8-2.7a active comm 8 ld msop 1 2.46 x4043m8-4.5a active comm 8 ld msop 1 2.46 x4043m8i active ind 8 ld msop 1 2.55 x4043m8i-2.7 active ind 8 ld msop 1 2.55 x4043m8i-2.7a active ind 8 ld msop 1 2.55 x4043m8i-2.7c7975 active ind 8 ld msop 1 x4043m8i-2.7t1c7168 active ind 8 ld msop t+r 1 2.55 x4043m8i-2.7t1c7975 active ind 8 ld msop t+r 1 2.53 x4043m8i-2.7t2 active ind 8 ld msop t+r 3 2.55 x4043m8i-2.7t6 active ind 8 ld msop 1 2.55 x4043m8i-4.5a active ind 8 ld msop 1 2.55 x4043m8iz active ind 8 ld msop 2 2.55 x4043m8iz-2.7 active ind 8 ld msop 2 2.55 x4043m8iz-2.7a active ind 8 ld msop 2 2.55 x4043m8iz-2.7t1 active ind 8 ld msop t+r 2 2.55 x4043m8iz-4.5a active ind 8 ld msop 2 2.55 x4043m8z active comm 8 ld msop 2 2.46 x4043m8z-2.7 active comm 8 ld msop 2 2.46 x4043m8z-2.7a active comm 8 ld msop 2 2.46 x4043m8z-4.5a active comm 8 ld msop 2 2.46 x4043m8zt1 active comm 8 ld msop t+r 2 2.46 x4043p active comm 8 ld pdip n/a 2.46 x4043p-2.7 active comm 8 ld pdip n/a 2.46 x4043p-2.7a active comm 8 ld pdip n/a 2.46 x4043p-4.5a active comm 8 ld pdip n/a 2.46 x4043pi active ind 8 ld pdip n/a 2.55 x4043pi-2.7 active ind 8 ld pdip n/a 2.55 x4043pi-2.7a active ind 8 ld pdip n/a 2.55 x4043pi-4.5a active ind 8 ld pdip n/a 2.55 x4043piz active ind 8 ld pdip n/a 2.55 x4043piz-2.7 active ind 8 ld pdip n/a 2.55
x4043piz-2.7a active ind 8 ld pdip n/a 2.55 x4043piz-4.5a active ind 8 ld pdip n/a 2.55 x4043pz active comm 8 ld pdip n/a 2.46 x4043pz-2.7 active comm 8 ld pdip n/a 2.46 x4043pz-2.7a active comm 8 ld pdip n/a 2.46 x4043pz-4.5a active comm 8 ld pdip n/a 2.46 x4043s8 active comm 8 ld soic 1 1.99 x4043s8-2.7 active comm 8 ld soic 1 1.99 x4043s8-2.7a active comm 8 ld soic 1 1.99 x4043s8-2.7at1 active comm 8 ld soic t+r 1 1.99 x4043s8-2.7t1 active comm 8 ld soic t+r 1 1.99 x4043s8-4.5a active comm 8 ld soic 1 1.99 x4043s8i active ind 8 ld soic 1 2.06 x4043s8i-2.5 active ind 8 ld soic 1 1.84 x4043s8i-2.7 active ind 8 ld soic 1 2.06 x4043s8i-2.7a active ind 8 ld soic 1 2.06 x4043s8i-2.7at1 active ind 8 ld soic t+r 1 2.06 x4043s8i-4.5a active ind 8 ld soic 1 2.06 x4043s8it1 active ind 8 ld soic t+r 1 2.06 x4043s8it2 active ind 8 ld soic t+r 3 2.06 x4043s8iz active ind 8 ld soic 1 2.06 x4043s8iz-2.7 active ind 8 ld soic 1 2.06 x4043s8iz-2.7a active ind 8 ld soic 1 2.06 x4043s8iz-2.7at1 active ind 8 ld soic t+r 1 2.06 x4043s8iz-4.5a active ind 8 ld soic 1 2.06 x4043s8izt1 active ind 8 ld soic t+r 1 2.06 x4043s8t1 active comm 8 ld soic t+r 1 1.99 x4043s8z active comm 8 ld soic 1 1.99 x4043s8z-2.7 active comm 8 ld soic 1 1.99 x4043s8z-2.7a active comm 8 ld soic 1 1.99 x4043s8z-2.7at1 active comm 8 ld soic t+r 1 1.99 x4043s8z-2.7t1 active comm 8 ld soic t+r 1 1.99 x4043s8z-4.5a active comm 8 ld soic 1 1.99 x4043s8zt1 active comm 8 ld soic t+r 1 1.99 x4043m8iz-2.7t2 coming soon ind 8 ld msop t+r 2 x4043s8izt2 coming soon ind 8 ld soic t+r 3 the price listed is the manufacturer's suggested retail price for quantities between 100 and 999 units. however, prices in today's market are fluid and may change without notice. msl = moisture sensitivity level - per ipc/jedec j-std-020 smd = standard microcircuit drawing description the x4043/45 combines four popular functions, power-on reset control, watchdog timer, supply voltage supervision, and block lock protect serial eeprom memory in one package. this
combination lowers system cost, reduces board space requirements, and increases reliability. applying power to the device activates the power-on reset circuit which holds reset /reset active for a period of time. this allows the power supply and oscillator to stabilize before the processor can execute code. the watchdog timer provides an independent protection mechanism for microcontrollers. when the microcontroller fails to restart a timer within a selectable time out interval, the device activates the reset /reset signal. the user selects the interval from three preset values. once selected, the interval does not change, even after cycling the power. the device?s low v cc detection circuitry protects the user?s system from low voltage conditions, resetting the system when v cc falls below the minimum v cc trip point. reset /reset is asserted until v cc returns to proper operating level and stabilizes. five industry standard vtrip thresholds are available, however, intersil?s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. the memory portion of the device is a cmos serial eeprom array with intersil?s block lock protection. the array is internally organized as x 8. the device features an 2-wire interface and software protocol allowing operation on an i 2 c bus. the device utilizes intersil?s proprietary direct write? cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. key f eatures selectable watchdog timer low v cc detection and reset assertion five standard reset threshold voltages adjust low v cc reset threshold voltage using special programming sequence reset signal valid to v cc = 1v low power cmos <20a max standby current, watchdog on <1a standby current, watchdog off 3ma active current 4kbits of eeprom 16-byte page write mode self-timed write cycle 5ms write cycle time (typical) built-in inadvertent write protection power-up/power-down protection circuitry protect 0, 1/4, 1/2, all or 16, 32, 64 or 128 bytes of eeprom array with block lock? protection 400khz 2-wire interface 2.7v to 5.5v power supply operation available packages 8 ld soic 8 ld msop 8 ld pdip pb-free plus anneal available (rohs compliant) related documentation datasheet(s): cpu supervisor with 4kbit eeprom parametric data
number of voltage monitors 1 v s range (v) 4.5 to 5.5 4.5 to 5.5 2.7 to 5.5 2.7 to 5.5 voltage threshold 1 4.62 (2.6%) 4.38 (3%) 2.92 (2.4%) 2.62 (2.7%) reset output type active high watchdog timer (s) off, 0.6, 0.2, 1.4 manual reset n bus interface i 2 c eeprom size (kbits) 4 battery montor and switchover n fault detection register n suffix -4.5a blank -2.7a -2.7 por (ms) 200 rtc function n application block diagrams digital projector frame grabber industrial ac industrial controls infusion pump inkjet printer laser printer related devices parametric table x4003 cpu supervisor x4005 cpu supervisor x4045 cpu supervisor with 4kbit eeprom x4163 16k, 2k x 8 bit; cpu supervisor with 16k eeprom x4165 16k, 2k x 8 bit; cpu supervisor with 16k eeprom x4323 cpu supervisor with 32k eeprom x4325 cpu supervisor with 32k eeprom x4c105 cpu supervisor with novram and output ports about us | careers | contact us | investors | legal | privacy | site map | subscribe | intranet ?2007. all rights reserved.

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